Designing a Stackup for High-Speed Design

The physical makeup of the board itself plays the dominant role in establishing impedances and signal propagation speeds. It can no longer be an afterthought if one wishes to assure signal integrity. Though your fabricator is happy to provide you with a stackup, you need to know what you want before approaching them.
This webinar will guide you through the process of verifying your stackup. The webinar will cover:

• Material section
  

• Differential pair width/pitch
  

• Optimal via geometry
  

We will use this information to perform a time-domain verification using the Simbeor Electromagnetic Analysis Tool. Attending this webinar will give you the tools and knowledge you need to confidently design your stackup and interconnect geometry for first-pass success.

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The accidental antenna and how to make one

There are antennas, and then there are accidental antennas. Accidental antennas are the noisemakers of your PCB design. They are created when the board's copper takes on a role beyond its job of connecting point A to point B.

If an accidental antenna did not wreak havoc on the test bench or with the initial prototype, their presence often would be felt during FCC testing, when the project is already a dollar short and a day late.

This webinar will examine accidental antennas and provide some guidance as to how to avoid creating them. The three objectives of this webinar:

• Does a properly created microstrip behave as an antenna?
  

• What changes can be made to increase/decrease such behavior?
  

• What makes a good shield?
  

As much as we would like to boil this down to simple "rules of thumb," some concepts should first be reviewed. We encourage you to review our recent publicly released videos that will provide additional information that you may find beneficial:


Transmission Line AC Impedance ???

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What is 50 Ohm Impedance? ????????

Watch the Video

Q&A from Webinar

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Practical Aspects of Signal Integrity - Part 1

"There are two kinds of engineers: those who have signal integrity problems and those that will." - Eric Bogatin


At Nine Dot Connects, we will be the first to admit that Signal Integrity (SI) analysis has not been one of our primary concerns. We believed that following "best practices" would be sufficient for all of our high-speed design needs for years. And it also seemed more cost-effective to do a respin or two rather than spend the money to purchase and learn advanced SI tools.

However, times change, and reality has reared its ugly head. Faster signal transitions, tighter layouts, lower voltage levels, costly high-density parts, and shorter production cycles are all conspiring to make SI analysis an absolute necessity for a successful product.

Lifecycle Insights (September 2018) found that the average number of respins was 2.9, and the average cost of a respin was an incredible $28,482.

In response, we have a webinar to present how SI analysis can be applied to real-world design examples. Tom Cassidy, who has years of experience doing high-speed design and layout, will present a series of common layout paradigms and how SI can be used to identify potential problems and provide solutions. The webinar will culminate with a finished DDR3 design, showing how SI analysis can help ensure a working layout the first time.

Although this webinar will use a board designed in Altium and analyzed in Cadence Sigrity, the concepts apply to any tier-one analysis tool.

Q&A from Webinar

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Practical Aspects of Signal Integrity - Part 2

"There are two kinds of engineers: those who have signal integrity?problems and those that will." - Eric Bogatin


In part one of our webinar on "Practical Aspects of Signal Integrity," Tom Cassidy provided the basic design concepts to consider when laying out a board for high-speed signals to ensure the signal's integrity. If you missed it, we encourage you to watch the recording of this webinar. The concepts presented build upon each other.

Watch Part 1

In part two, Tom will be presenting on several design use cases, including:

• Reference Planes
  

• Stripline vs. Microstrip
  

• Differential Pairs
  

• Termination
  

• Crosstalk
  

• Fly-by vs. T-Branch
  

• Complete DDR3 layout
  

Although this webinar will use a board designed in Altium Designer and analyzed in Cadence Sigrity, the concepts apply to any tier-one analysis tool.

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Practical Aspects of Signal Integrity - Part 3

"There are two kinds of engineers: those who have signal integrity problems and those that will." - Eric Bogatin


In parts 1 and 2 of our webinar on "Practical Aspects of Signal Integrity," Tom Cassidy provided the basic design concepts to consider when laying out a board for high-speed signals to ensure the signal's integrity. If you missed one or both, we encourage you to watch the recording of these webinars. The concepts presented build upon each other.

Watch Part 1

Watch Part 2

In Part 3 of this webinar series, Tom will present the simulation and analysis of a functional FPGA-based DDR3 memory design. He will also examine some common layout paradigms inherent to DDR3 and explore their signal integrity implications.

• Xilinx Zynq FPGA and Micron DDR3 Memory
  

• "Power-aware" Simulation and Analysis
  

• JEDEC Compliance Reports
  

• Signal Termination
  

• Differential Pair Routing Concerns
  

• Alternate Routing Paradigms
  

Although this webinar will use a board designed in Altium Designer and analyzed in Cadence Sigrity, the concepts apply to any tier-one analysis tool.

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Practical Aspects of Serial Communications - Part 4

Serial communication is a lot like the display of cascading dominoes. The cascade (energy propagating from one end to the other) relies upon each domino falling in the right direction with enough momentum to cause the next domino to fall. Serial communication is not much different when propagating an energy wave, which we call a "signal," along a trace. But unlike cascading dominoes, which make for interesting Rube Goldberg machines, we should not have to hold our breath and hope for the best regarding the signal integrity of our serial communication lines on a PCB.

Part 4 of the Nine Dot Connects "Practical Aspects" webinar series will focus on serial communications. We will cover several communication paradigms, including SPI, PCIe, and USB3.0, using Cadence's Sigrity toolset to demonstrate these concepts. Additionally, this webinar will explore how high-speed serial bus design aspects cross over into the advanced parallel design world.

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Beyond a Heatsink - Thermal Considerations in PCB Design

'Thermal' is a design item that we might expect only the mechanical engineers to consider and use flow simulation tools such as those found in SOLIDWORKS and other mechanical design tools. One must remember that component selection and placement tremendously impact the simulation results. The old saying 'nip it in the bud' is very germane here, and catching thermal issues early is a perfect example.

Understanding thermal issues don't require a degree or training in thermodynamics. It simply understands what needs to be exported from your PCB design and sets up the simulation with the proper tools.

This webinar will explore the workflow for testing thermal flow for a PCB. This webinar will be presented by Bill Dempsey, a PCB design engineer who has provided thermal simulation services to multiple clients.

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Power Distribution Network & Power Integrity

Though signals tend to focus on impedance issues, the power distribution network (PDN) on the board is just as susceptible to impedance. The PCB layer stack-up is a capacitor all its own, and with the addition of bypass capacitors and inductors on the board, the ability to distribute power to avoid power starvation or to reduce ripple becomes an integral part of the design.

Topics include:

• The power distribution network and how impedances interrupt and starve components of the power they require.
  

• Dive deeper into the impedances caused by capacitors and inductors and, more importantly, how they interact.
  

• How to manage the impedance by a careful selection of capacitors.
  

We will use the iCD PDN Planner tool to see the results as we present them visually.

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High-Speed Design (Signal Integrity) in Altium Designer

The term 'High-Speed' design, a popular term in the EDA industry, is used by many EDA companies to express the idea that their tool has functionality that makes it better at producing electrically stable designs. However, like analog design, high-speed design is a part of art form and science. Though Altium Designer provides functionality to assist in high-speed design, it still requires an understanding to apply those capabilities properly.

Altium Designer provides core capabilities to assist in analyzing, constraining and routing high-speed interconnects.

In this webinar, we will explore:

• The Layer Stack Manager, as it relates to proper stack up for design
  

• Noise and how to mitigate it through proper layer stack up
  

• The Signal Integrity tools that Altium provides, including cross-talk and reflections
  

• The Signal Integrity rules and how they relate to Signal Integrity capabilities
  

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Altium SPICE

This video is a brief overview of the SPICE capability in Altium Designer. It provides a general understanding of how users would add models to the components and set up and run the analysis.

Altium provides several SPICE-specific libraries that a user will need to provide a stimulus to the circuit (i.e., VDC, sine waves, pulses, etc.). They are generally located in the example directory created during the installation of Altium Designer. This directory path will be similar to C:UsersPublicDocumentsAltiumADxx.xLibrarySimulation, where ADxx.x is a version number.

The 5 libraries provided (all of which are Integrated Libraries):

• Simulation Math Function
  

• Simulation PSPICE Functions
  

• Simulation Sources
  

• Simulation Special Functions
  

• Simulation Transmission Line
  

Install these libraries as you would with any library in Altium.

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iCD's PDN Planner

In the high-speed design, the focus tends to be on signal integrity aspects of the traces; however, the power planes are also subject to integrity issues at high frequencies. The fact is that a board's Power Distribution Network (PDN) is more than just large areas of copper for the power and ground. Even the bypass capacitors chosen may not only fail to mitigate noise at specific frequencies, but the improper selection of the capacitor values can also contribute to the noise levels. As a result, a board will not only have issues of its own but will be at the mercy of the external environment in which it must operate.

The ICD PDN planner was developed to allow the layout designer to select bulk and bypass capacitor values that optimally provide low impedance paths for noise at all frequencies of concern on the PDN. Since the PDN planner can access the ICD stack-up planner's data, the board's effects can be added to the field solver to provide accurate results.

The ICD PDN Planner provides over 5,600 capacitors in the library. More will be added as they become available. The user can add capacitors to the library as well.

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When do you simulate?

There seems to be an increasing number of simulation tools being introduced to the market as of late.
Power, signal integrity, timing, thermal, EMI, etc. Do you need them? Should you use them? Are you missing out on something that can improve the design?

Simulation tools are an investment in both time and money. While some may provide instant answers or verification, others may require time to understand the tool, set up the initial conditions, and interpret the results.

This month, we will take a deeper look into this concept of simulation:

• Where do simulations fit into the design process and why
  

• Circuit sim vs. Layout sim vs. structure sim
  

• Example of software types and applications
  

• Pitfalls and misconceptions
  

Please note that this is not a webinar to compare tools but to understand the different types of simulations and their added value (or lack thereof).