"There are two kinds of engineers: those who have signal integrity problems and those that will." - Eric Bogatin
In parts 1 and 2 of our webinar on "Practical Aspects of Signal Integrity," Tom Cassidy provided the basic design concepts to consider when laying out a board for high-speed signals to ensure the signal's integrity. If you missed one or both, we encourage you to watch the recording of these webinars. The concepts presented build upon each other.
In Part 3 of this webinar series, Tom will present the simulation and analysis of a functional FPGA-based DDR3 memory design. He will also examine some of the common layout paradigms inherent to DDR3 and explore their signal integrity implications.
Xilinx Zynq FPGA and Micron DDR3 Memory
"Power-aware" Simulation and Analysis
JEDEC Compliance Reports
Differential Pair Routing Concerns
Alternate Routing Paradigms
Although this webinar will be using a board designed in Altium Designer and analyzed in Cadence Sigrity, the concepts apply to any tier-one analysis tool.