Designing a Stackup for High-Speed Design

The physical makeup of the board itself plays the dominant role in establishing impedances and signal propagation speeds. It can no longer be an afterthought if one wishes to assure signal integrity. Though your fabricator is happy to provide you with a stackup, you need to know what you want before approaching them.
This webinar will guide you through the process of verifying your stackup. The webinar will cover:

• Material section
  

• Differential pair width/pitch
  

• Optimal via geometry
  

We will use this information to perform a time-domain verification using the Simbeor Electromagnetic Analysis Tool. Attending this webinar will give you the tools and knowledge you need to confidently design your stackup and interconnect geometry for first-pass success.

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PCB Translation - "Invisible Insanity"

The famous science fiction writer Isaac Asimov was quite fond of telling jokes. He once joked about a computer developed to translate between English and Russian. As a test case, they decided to input the phrase 'out of sight, out of mind.'? They immediately took the result in Russian and fed it back into the computer. The result: 'invisible insanity.'? This, at times, describes the process of translating a PCB design from one tool to another.

EDA tools are like spoken languages. As a result, the effort to migrate a design between tools is rarely simple. Several 'gotchas' need to be realized and avoided and nuances to be understood and managed. This assumes that one could get the bulk of the design translated, to begin with.

The purpose of this webinar is to walk through a translation performed on a Beaglebone board. While this will be imported into Altium, this is a must-see for anyone who is either:

• Contemplating a move to another software tool, or
  

• Wanting to take an existing board and translate it to the tool of their interest, or
  

• Wanting to hire a contractor who uses another tool.
  

Download Translation Checklist

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When Designs and Designers Need to Be "Flexible"

There have been many webinars focused on rigid-flex design. Many of these webinars come from manufacturers of rigid-flex boards. They explain what is necessary for us to achieve success in manufacturing these boards. We have also seen a few webinars from ECAD software companies showing us their tools' various capabilities.

What is missing? They are rigid-flex considerations from a designer's point of view. Our tools can do it, and our manufacturing can create it, but the real question is - how do we design it? That will be the focus of our upcoming webinar.

We will explore the following rigid-flex design topics:

• Board outline and bending
  

• Design rules about the flex circuit
  

• Component placement on a flex circuit
  

• Copper types on a flex circuit (pours, fill, and vias)
  

• Routing on a flex circuit
  

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Power Distribution Network & Power Integrity

Though signals tend to focus on impedance issues, the power distribution network (PDN) on the board is just as susceptible to impedance. The PCB layer stack up is a capacitor all its own, and with the addition of bypass capacitors and inductors on the board, the ability to distribute power to avoid power starvation or to reduce ripple becomes an integral part of the design.

Topics include:

• The power distribution network and how impedances interrupt and starve components of the power they require.
  

• Dive deeper into the impedances caused by capacitors and inductors and more importantly, how they interact.
  

• How to manage the impedance by a careful selection of capacitors.
  

We will use the iCD PDN Planner tool to see the results as we present them visually.

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Intuitive Stack-up Planning & Impedance Control

How do you intuitively engineer good impedance-controlled PCB stack-up and routing plans for each new design which meets all of their specific impedance control design requirements?

• Search on the Internet?
  

• Do hand calculations?
  

• Ask a friend?
  

• Always force the design into the same one or two because they worked in the past?
  

• Buy a costly and complex tool like Polar?
  

• 'Feel' the best solution
  

• Hire some 'expert' to do it?
  

Can you intuitively visualize and understand what it's doing and how to reliably use it?

How do you efficiently approach gathering the raw data to make the final choices?

As signal speeds increase, the shortcomings of materials (like FR-4) become critical. Dielectric constants aren't constant, resulting in dispersion. Loss increases and is frequency dependent resulting in signal degradation over longer runs. Gathering information on lots of materials, tabulating all the information at various frequencies along with the specific thicknesses available, selecting optimal materials, and adjusting stack-ups to compensate can be very time-consuming and error-prone.

In this video, we will intuitively show you how various elements of a PCB's structure and routing affect the electromagnetic fields and turn the couplings, energies, and characteristic impedance of traces on it. Practical suggestions, methods, alternatives, and solutions will be discussed.

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Test Points - Before Layout and Way Beyond Manufacturing

Design for Test (DFT) does not occur naturally in design, especially with the advent of BGAs and components so small that one must use tweezers to grasp them, let alone probe them. Yet, the test points are one of the most straightforward items to add to a design for the test in fabrication, assembly, and labs.

In this webinar, we will cover:

• The benefits of test points
  

• Recommended copper structures
  

• The various approaches to using test points within Altium Designer
  

We provided the Altium PCB project used in the video. Feel free to download it.

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High-Speed Topic: The stuff that makes up signal integrity - AC Impedance

We introduced the concept of impedance as it relates to both cables and printed circuit boards. However, that conversation was kept concerning Direct Current (DC) to establish the fundamental concept of impedance. If you missed this webinar or would like to refresh yourself on the topic, please check out the link and request the video recording:

DC Impedance Video

In this video, we will continue to discuss impedance from the AC perspective. This is imperative since high-speed signal integrity entirely relies on knowing the impedance issues and requirements.

We will compare AC and DC impedances during this video, take a closer look at the composition of a square wave, delve into the S-parameters (scatter parameters), S12 for isolation, and S21 for insertion loss, and then see how these aspects apply to the PCB.

Sean Kelly, one of the senior RF/high-speed engineers here at Nine Dot Connects, will be presenting.

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High-Speed Topic: What is meant by a 50-ohm impedance?

In our past videos, we have discussed characteristic impedance related to the layer stack-up of the PCB. However, we have yet to address the notion of impedance itself. Impedance has always been part of the signal traces on a PCB but is not necessarily a concern. With high-speed designs becoming more prevalent and significantly faster-rising edge times now common on all digital components (even the classic 7400 logic gate series), understanding impedance is becoming a critical concern. Many of the intermittent failures one may experience can be traced back to impedance issues.

In this deep dive, the focus will be on the fundamentals of impedance:

• Review the classic approach of the voltage/current relationship and explain why the inductance to capacitance relationship creates the same kind of relationship, hence the term 'characteristic impedance.'
  

• Discuss the three functions of impedance: power transfer, reflections, and radiation. Understanding and managing these three critical functions can help avoid attenuation, signal distortion, and cross-talk.
  

• Review of T-line theory as an infinite transmission line
  

Sean Kelly will give this presentation. Sean has been in the electronics industry for 30 years, with 20 years of experience in PCB design. Also, Sean is an instructor and consultant on topics such as high-speed design and RF.

Q&A's from Webinar

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Vias: Blind, Buried and Beyond

The Z-direction on a PCB multi-layer is remarkably restrictive. We do not draw copper from one layer to the next. We must make use of a copper structure called the via. Over time, more via options have been made available to accommodate small components and densely populated boards.

In this video, we will discuss:

• Sanity check - Make sure that the desired via type works with the stack up
  

• Annular rings - the equation to ensure the right fit/hit
  

• Explore non-traditional vias types - microvias, back drilled vias, vias-in-pad
  

• Documentation - what automatically gets generated and what needs to be provided as a fabrication note
  

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Deep Dive - Capacitors

For many of us, the introduction to capacitors was in the form of equations related to the charge plates. When selecting sizes and types of capacitors for real designs, much of it tends to be based on experiences, tribal knowledge, and copying and pasting from existing similar designs.

We will present a deep dive webinar on CAPACITORS. Our discussion includes:

• The uses for capacitors
  

• The various configurations
  

• The various materials and their advantages/disadvantages
  

Our PCB expert will present this deep dive, Jeff Condit, who has 40+ years of experience in the PCB design domain.

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Deep Dive - Inductors (Prologue)

Inductors were widely used decades ago, for they were far easier to make than capacitors. A good deal of inductors was wound by the engineer or technician. Over time, capacitors took on popularity that even encouraged engineers to avoid inductors whenever possible.

In this webinar, we will dig deep into the concepts and uses for inductors, revisiting known circuits that use inductors and exploring other ways of using them that may not be so obvious.

A review of the fundamentals will also be given, touching on eddy currents and hysteresis.

This Webinar will be presented by Jeff Condit, whose 40+ years of industry knowledge includes a great deal of winding experience and using inductors in many of his power and analog projects.

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Deep Dive - Inductors

Inductors were widely used decades ago, for they were far easier to make than capacitors. A good deal of inductors was wound by the engineer or technician. Over time, capacitors took on the popularity that even encouraged engineers to avoid inductors whenever possible.

In this webinar, we will dig deep into the concepts and uses for inductors, revisiting known circuits that use inductors and exploring other ways of using them that may not be so obvious.

A review of the fundamentals will also be given, touching on eddy currents and hysteresis.

This Webinar will be presented by Jeff Condit, whose 40+ years of industry knowledge includes a great deal of winding experience and using inductors in many of his power and analog projects.

Q&A's from Webinar

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Deep Dive - Vias

If you have attended our webinars in the past, we are always pressed to keep the presentations under an hour. With any given topic, there is far more information than we can present. How often have we said, "There's more to it, but" or "We don't have the time to go into detail?"

Therefore, we will hold our first deep dive session. From the feedback we have received from our webinar on PCB stack-ups, there is an interest in the topic of vias, mainly their purpose, types of vias available, stack-up, DFM, and layout considerations.

The format of this webinar is simple enough - we will speak on the topic for 20 minutes. Though we may show pictures to help illustrate a point, this is not a PowerPoint or formal presentation. We want this webinar to be driven by participant questions.

Our PCB expert will present this deep dive, Jeff Condit, who has 40+ years of experience in the PCB design domain.

Q&A's from Webinar

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iCD's Design Integrity

When it comes to high-speed design, the name of the game is understanding and controlling impedance.

At first glance, you may wonder why ICD put together software that seems to address 2 nearly unrelated areas. The stack-up planner addresses the layers. The PDN planner addresses the use of capacitors. What gives?

When we look at the high-speed design, we are dealing with the effect of impedance on the traces and the power provided to the board. The trace impedances are heavily influenced by the layer stack up.

On the power planes, we also deal with impedances. Any noise that makes its way onto the Power Distribution Network (PDN) (a.k.a the power planes) needs to be given a low impedance path to the ground plane, regardless of the noises' frequencies. Thus the need to determine which values of capacitors are needed, what kind, and how many. The PDN Planner provides over 6500 capacitors in the library. More will be added as they become available. The user can add capacitors to the library as well.

The iCD stackup planner provides accurate impedance information through its built-in field solver. By using the information in the stack-up planner, the PDN planner can, in turn, provide accurate information for all noise frequencies of concern. With the iCD stack up the planner, the user can access a library of over 23,230 materials (core, prepreg, and solder mask) up to 100 GHz.

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Regarding The Price of The PowerStack Suite

When one considers the iCD PowerStack Suite cost versus the engineering labor cost to manually develop a complex stack-up solution, the Return On Investment (ROI) is worth further consideration.

Consider the following calculations. The ICD PowerStack Suite is $4,995. According to the site https://www.sokanu.com/careers/electrical-engineer/salary as of September 2016, the average salary of a senior engineer is ~$93,000/year. $4,995 equates to a little less than 3 weeks of engineering labor. Granted, one who does PCB stackups all the time or a well-seasoned engineer could take less time. However, few engineers are experts in layer stack-ups, and more so, few engineers who are trained in such matters may only use this knowledge two or three times a year. In engineering, the old saying “use it or lose it” rings true.

A layer stack-up for complex designs is not trivial. The days of simply using FR-4 for the dielectric are over. Anyone putting together a complex board has to do some research into the various materials. Unlike FR-4, several different materials must be used, each with its advantages and disadvantages. The research includes downloading the spec sheets, reading them thoroughly, making decisions, and verifying the proposed stack-up with the fabricator. That alone can take a couple of days on a complex board.

Calculations for impedance, trace spacing, and trace width are not trivial. They require field solvers for accuracy. Even if the stack-up is manufacturable, failure to get the calculations right will be very costly. Scrapped boards and the labor costs for redesign due to erroneous impedance and trace values are tens of thousands of dollars.

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iCD's Stackup Planner

It may not be obvious; however, the layer stackup ultimately influences the trace impedances. The question is, how does one derive rules for constraints such as trace space and trace width? Some EDA tools provide equations, while others do not. In the end, this is not something that can be guessed. That's where the iCD Stackup Planner comes in.

One should always consult their fabricator on the stack-up from the start of the PCB layout. Sure, they can provide the impedance numbers for you in addition to a stackup itself. However, there are many variables to play with, and sometimes, it makes sense to investigate other materials, dielectric thicknesses, different heights, trace widths, and trace spacing.

With the iCD Stackup Planner, the user has access to a library of over 23,230 materials (core, prepreg, and solder mask) up to 100 GHz. The frequency capability of the materials is also essential. When placing a core material, it should have the same weight of copper on both sides. Although one can specifically order any combo (at a price), it is economical to use 1oz or 1/2 oz on each side.

Also, with its built-in field solver, the iCD can provide accurate impedance measurements for each layer in addition to providing rules such as trace space and trace width. In the end, you not only control what you believe to be the optimal stack-up, but you also have the ability to have an intelligent conversation with your fabricator.

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Regarding The Price of The Stackup Planner

When one considers the iCD Stackup Planner's cost versus the engineering labor cost to manually develop a complex stack-up solution, the Return On Investment (ROI) is certainly worth further consideration.

Consider the following calculations. The iCD Stackup Planner is $2,995. According to the site https://www.sokanu.com/careers/electrical-engineer/salary as of September 2016, the average salary of a senior engineer is ~$93,000/year. $2,995 equates to a little less than 2 weeks of engineering labor. Granted, one who does PCB stackups all the time or a well-seasoned engineer could take less time. However, few engineers are experts in layer stackups, and more so, few engineers who are trained in such matters may only use this knowledge two or three times a year. The old saying "use it or lose it" rings true in engineering.

A layer stack-up for complex designs is not trivial. The days of simply using FR-4 for the dielectric are over. Anyone putting together a complex board has to do some research into the various materials. Unlike FR-4, several different materials must be used, each with its advantages and disadvantages. The research includes downloading the spec sheets, reading them thoroughly, making decisions, and verifying the proposed stack-up with the fabricator. That alone can take a couple of days on a complex board.

Calculations for impedance, trace spacing, and trace width are not trivial. They require field solvers for accuracy. Even if the stack-up is manufacturable, failure to get the calculations right will be very costly. Scrapped boards and the labor costs for redesign due to erroneous impedance and trace values are tens of thousands of dollars.

See Product Overview

Request Information

iCD's PDN Planner

In the high-speed design, the focus tends to be on signal integrity aspects of the traces; however, the power planes are also subject to integrity issues at high frequencies. The fact is that a board's Power Distribution Network (PDN) is more than just large areas of copper for the power and ground. Even the bypass capacitors chosen may not only fail to mitigate noise at specific frequencies, but the improper selection of the capacitor values can also contribute to the noise levels. As a result, a board will not only have issues of its own but will be at the mercy of the external environment in which it must operate.

The ICD PDN planner was developed to allow the layout designer to select bulk and bypass capacitor values that optimally provide low impedance paths for noise at all frequencies of concern on the PDN. Since the PDN planner can access the ICD stack-up planner's data, the board's effects can be added to the field solver to provide accurate results.

The ICD PDN Planner provides over 5,600 capacitors in the library. More will be added as they become available. The user can add capacitors to the library as well.

See Product Overview

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