It may not be obvious; however, the layer stackup completely influences the trace impedances. The question is, how does one derive rules for constraints such as trace space and trace width? Some EDA tools provide equations, while others do not. In the end, this is not something that can be guessed. That's where the iCD stack up planner comes in.
One should always consult their fabricator on the stack up from the very start of the PCB layout. Sure, they can provide the impedance numbers for you in addition to a stack-up itself. However, there are many variables to play with, and sometimes, it makes sense to investigate other materials, dielectric thicknesses, different heights, different trace widths, and different trace spacings.
With the iCD stackup planner, the user has access to a library of over 33,250 materials (core, prepreg, and solder mask) up to 100 GHz. The frequency capability of the materials is also important. When placing a core material, it should have the same weight of copper on both sides. Although one can specifically order any combo (at a price), it is economical to use 1 oz or 1/2 oz on each side.
Also, with its built-in field solver, the ICD can provide accurate impedance measurements for each layer in addition to providing rules such as trace space and trace width. In the end, you not only control what you believe to be the optimal stack up, but you also have the ability to have an intelligent conversation with your fabricator.
Stackup Planning Articles
Barry Olney, the owner of iCD and the developer of the iCD product, has over 40 years of experience in PCB design and his knowledge of EDA tools. Barry writes a column on PCB high-speed design for PCB Design Magazine. Links to past articles are provided below. These articles are a wealth of engineering information as they relate to high-speed design issues.
When one considers the ICD Stackup Planner's cost versus the engineering labor cost to develop a complex stack-up solution manually, the Return On Investment (ROI) is certainly worth further consideration.
Consider the following calculations. According to the site https://www.sokanu.com/careers/electrical-engineer/salary as of September 2016, the average salary of a senior engineer is ~$93,000/year. The cost of an iCD Stackup Planner is a little less than 2 weeks of engineering labor. Granted, one who does PCB stackups all the time or a very well-seasoned engineer could take less time. However, few engineers are experts in layer stack-ups, and more so, few engineers who are trained in such matters may only use this knowledge two or three times a year. In engineering, the old saying 'use it or lose it' rings true.
A layer stackup for a complex design is not trivial. The days of simply using FR-4 for the dielectric are over. Anyone putting together a complex board has to do some research into the various materials. Unlike FR-4, several different materials must be used, each with its advantages and disadvantages. The research includes downloading the spec-sheets, reading them thoroughly, making decisions, and verifying the proposed stack up with the fabricator. That alone can take a couple of days on a complex board.
Calculations for impedance, trace spacing, and trace width are not trivial. They require field solvers for accuracy. Even if the stack up is manufacturable, failure to get the calculations right will be very costly. Scrapped boards and the labor costs for redesign due to erroneous impedance and trace values are tens of thousands of dollars.