In the high-speed design, the focus tends to be on signal integrity aspects of the traces; however, the power planes are also subject to integrity issues at high frequencies. The fact of the matter is that the Power Distribution Network (PDN) of a board is more than just large copper areas for the power and ground. Even the bypass capacitors chosen may not only fail to mitigate noise at certain frequencies, but the improper selection of the capacitor values can also contribute to the noise levels. As a result, a board will not only have issues of its own but will be at the mercy of the external environment in which it must operate.
The ICD PDN planner was developed to give the layout designer the ability to select bulk and bypass capacitor values that will optimally provide low impedance paths for noise at all frequencies of concern on the PDN. Since the PDN planner can access the ICD stack-up planner's data, the effects of the board can be added to the field solver to provide accurate results.
The ICD PDN Planner provides over 5,650 capacitors in the library. More will be added as they become available. The user can add capacitors to the library as well.
PDN Planning Articles
Barry Olney, the owner of iCD and the developer of the iCD product, has over 40 years of experience in PCB design and his knowledge of EDA tools. Barry writes a column on PCB high-speed design for PCB Design Magazine. Links to past articles are provided below. These articles are a wealth of engineering information as they relate to high-speed design issues.