The iCD Design Integrity software incorporates the Stackup, PDN and CPW Planner plus a myriad of new functionality specifically developed for high-speed PCB design.
When it comes to high speed design, the name of the game is understanding and controlling impedance…
At first glance, you may wonder why ICD put together software that seems to address 2 nearly unrelated areas. The stack up planner addresses the layers. The PDN planner addresses the use of capacitors. What gives?
When we really look at high speed design, we are dealing with the issue of the effect of impedance, both on the traces and on the power provided to the board. The trace impedances are heavily influenced by the layer stack up.
On the power planes, we also deal with impedances. Any noise that makes its way onto the Power Distribution Network (PDN) (a.k.a the power planes) needs to be given a low impedance path to the ground plane, regardless of the frequencies of the noises. Thus the need to determine which values of capacitors are needed, what kind, and how many. The PDN Planner provides over 5,650 capacitors in the library. More will be added as they become available. The user can add capacitors to the library as well.
The iCD Stackup Planner provides accurate impedance information through its built-in field solver. By using the information in the stack up planner, the PDN planner can, in turn, provide accurate information for all noise frequencies of concern. With the iCD Stackup Planner, the user has access to a library of over 33,250 materials (core, prepreg, and solder mask) up to 100 GHz.
"I am very pleased with the recent CPW update, as it will greatly help me keep as much copper as possible without impacting signal integrity.
All in all, please pass my complements to the chef. It's a very handy tool so far, and it has been proven time and again by several board houses that are impressed with how well my supplied geometries match the impedance goals - and there has been no complaint whatsoever with the Excel output from the tool. The board manufacturers seem to like having such a well-organized stackup description that they can use."
Consultant - Global Technical Systems
Stackup & PDN Planning Articles
Barry Olney, the owner of iCD and the developer of the iCD product, has over 40 years experience in the field of PCB design in addition to his knowledge of EDA tools. Barry writes a column on PCB high speed design for PCB Design Magazine. Links to past articles are provided below. These articles are a wealth of engineering information as they relate to high speed design issues.
When one considers the cost of the iCD Design Integrity versus the engineering labor cost to develop a complex stack-up solution manually, the Return On Investment (ROI) is certainly worth further consideration.
Consider the following calculations. According to the site https://www.sokanu.com/careers/electrical-engineer/salary as of September 2016, the average salary of a senior engineer is ~$93,000/year. The cost of an iCD Design Integrity little more than 3 weeks of engineering labor. Granted, one who does PCB stackups all the time or a very well-seasoned engineer could take less time. However, few engineers are experts in layer stack ups and more so, few engineers who are trained in such matters may only use this knowledge two or three times a year. In engineering, the old saying “use it or lose it” rings true.
A layer stack up for a complex designs is not trivial. The days of simply using FR-4 for the dielectric are over. Anyone putting together a complex board has to do some research into the various materials. Unlike FR-4, several different materials must be used, each with their advantages and disadvantages. Research includes downloading the spec-sheets, reading them thoroughly, making decisions, and then verifying the proposed stack up with the fabricator. That alone can take a couple days on a complex board.
Calculations for impedance, trace spacing and trace width are not trivial. They require field solvers for accuracy. Even if the stack up is manufacturable, failure to get the calculations right will be very costly. Scrapped boards and the labor costs for redesign due to erroneous impedance and trace values is in the tens of thousands of dollars.