Design Validation Roadshow

November 5, Houston, TX - November 6, 2014, Austin, TX

Fall is already here, and it is time for our semiannual Technology Roadshows in Texas. We are conducting design validation seminars in Houston and Austin. We will cover the tools in our seminar, but more importantly, we will cover methodology and design best practices. After all, Nine Dot Connects a design services provider, not just a regional Altium VAR. You will leave our design seminar with useful techniques that you can apply in your high-speed digital designs. We will cover 4 key topics that are critical to producing reliable, working hardware:

1) High-Speed Design Techniques Using Altium Designer & In-Circuit Design for Design Validation
- How to mitigate noise through proper layer stack up
- Computation of multiple differential pair definitions per layer
- Validate that your PCB stack-up & targeted materials are appropriate for hitting the trace impedance targets before completing the routing and sending the design to the fabricator for assessment
- Instantly analyze the Voltage Regulator Module, PCB Substrate - include plane resonance, bulk bypass, and decoupling capacitors simultaneously to solve parameters for the desired effective impedance of the Power Distribution Network
- Quit guessing at bypass and decoupling capacitor value and placement
- Make efficient use of Altium Designer's robust design rule checking capability for high-speed design

2) PCB Design Best Practices for Reliable Manufacturing
Jim Pierce, Application Engineering Manager of Axiom Electronics, presents a standardized process for reducing the risk associated with product design and manufacturability. This process uses standardized methods to reduce variables and measure results throughout the manufacturing process to decrease cost and improve quality and reliability. Jim has three decades of experience as a PCB designer. He has many years of experience in the DFM arena, having worked for several years at Axiom Electronics and DFW Test before that.

3) Ensuring That Your Electrically Robust Design Will Be Optimally Manufacturable Using DFM Validation
Though the design rule checkers in a PCB layout tool assist with manufacturing requirements, the design will eventually be translated into the ODB++ or Gerber format. Like any translation, some limitations do not render a perfect copy. Also, PCB design rules are focused on copper connectivity of the netlist, not necessarily manufacturing limitations. We will show you how you can analyze your PCB design to optimize your design's manufacturability before sending it to the contract manufacturer. This analysis will help you reduce yield loss, increase your product's life in the field, reduce cost, reduce manufacturing time, and ultimately, de-risk your product's production and deployment.

4) Identify Tolerance Violations with E3.eCheck
John Molloy, Zuken E3 director, presents a key feature within E3 Cable & Harness Design tool - eCheck. Component and wire tolerance violations can lead to design errors causing safety issues in the field and lead to recalls for vehicles and equipment. Correcting issues at this stage of the product lifecycle is very expensive. John will explore the benefits of electrically aware design and show how E3.eCheck can help with the following:

- Detect tolerance violations
- Optimize wire gauge to save weight and costs
- Analyze designs fast and efficiently
- Processes to implement to ensure operation within safety levels

Please fill out the form below to request information from previous seminars.