Test Engineers Must Join ASIC Flow Early

 

As a young engineer, it was a goal of mine to publish an article. Fortunately, Tality had incentives that encouraged such activity. This represents my first ever published paper.


When I started my career in ASICs just after college, I was hired into the Test and Prototyping group at Cadence. The job of this group was to test the real silicon that was being designed by both our customers and by our design groups. I have to admit that I felt that I had been a bit misled by the job description. I had just resigned a position at Aerospace Corporation in which I was responsible for “cradle to grave” product development. The idea of having to test someone else’s design work seemed rather odd to me. As far as I was concerned, if ya built it, you tested it!

In looking back, it was a well needed education in design flows. What I learned on the test floor has served me rather well, even to this day. I have a profound respect for test and debug, especially after witnessing my fair share design mishaps throughout my career in all design environments – ASIC, PCB and system.

I eventually made my way to the ASIC design group at Tality. With knowledge of the test floor, I was rather conscientious about designing silicon with testability in mind. I also found that I was one who had to educate my colleagues on the needs for the test floor, for it was rare to have a test engineer join the ranks of the designers.

With Tality’s incentives to write, I produced this write up which was submitted to EE Times for publication in 2002. It was published in its digital edition and is still available on the web.

Title: Test Engineers Must Join ASIC Flow Early
Author: Paul Taubman
Representing: Tality Corporation
Published by: EE Times
Date of Publication: February 2012

Download EE Times Paper

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